Shift register realizations of asynchronous sequential machines

Shift Register Realizations of Asynchronous Sequential Machines

Unitary Shift-Register Realizations of Sequential Machines

On Single-Loop Realizations of Sequential Machines

This paper is concerned with the problem of reMizing a sequential machine M by a sequential circuit with a single feedback loop carrying a binary signal. To find such a realization, one must find a binary total-state partit ion, which can be used for feedback, for the flow table T of M or for some expanded version of T. A method is presented for testing whether a given flow table possesses a fe...

On Shift Register Realization of Sequential Circuits

Realizing a sequential machine with shift registers is an attractive approach to the design for testability. It requires little extra circuit for scan and since feed-backs are always to the rst ip-op of a shift register test generation is expected to be easier than that for circuits with unstructured feedbacks. Though the shift register realization of sequential machines was studied by several ...

Realizations of parallel and multibit-parallel shift register generators

In this paper, we consider how to realize the parallel shift register generators (PSRG) and mutibit PSRG’s, which can be directly used for parallel frame synchronous scrambling (FSS) in the bitand multibit-interleaved multiplexing environments. We first describe the structure of PSRG’s in terms of three parameters—the state transition matrix, the initial state vector, and the generating vectors...